Perspectives - Very Low-Cost, Low-Power Servers

Saturday, November 20, 2010

I’m interested in low-cost, low-power servers and have been watching the emerging market for these systems since 2008 when I wrote CEMS: Low-Cost, Low-Power Servers for Internet Scale Services (paper, talk). ZT Systems just announced the R1081e, a new ARM-based server with the following specs:

· STMicroelectronics SPEAr 1310 with dual ARM® Cortex™-A9 cores

· 1 GB of 1333MHz DDR3 ECC memory embedded

· 1 GB of NAND Flash

· Ethernet connectivity

· USB

· SATA 3.0

It’s a shared infrastructure design where each 1RU module has 8 of the above servers. Each module includes:

· 8 “System on Modules“ (SOMs)

· ZT-designed backplane for power and connectivity

· One 80GB SSD per SOM

· IPMI system management

· Two Reatek 4+1 1Gb Ethernet switches on board with external uplinks

· Standard 1U rack mount form factor

· Ubuntu Server OS

· 250W 80+ Bronze Power Supply

Each module is under 80W so a rack with 40 compute modules would only draw 3.2kw for 320 low-power servers for a total of 740 cores/rack. Weaknesses of this approach are: only 2-cores per server, only 1GB/core, and the cores appear to be only 600 Mhz (http://www.32bitmicro.com/manufacturers/65-st/552-spear-1310-dual-cortex-a9-for-embedded-applications-). Four core ARM parts and larger physical memory support are both under development.

Competitors include SeaMicro with an Atom based design (SeaMicro Releases Innovative Intel Atom Server

) and the recently renamed Calxeda (previously Smooth-Stone) has an ARM-based product under development.

Other notes on low-cost, low-powered servers:

· SeaMicro Releases Innovative Intel Atom Server

· When Very Low-Power, Low-Cost Servers don’t make snese

· Very Low-Power Server Progress

· The Case for Low-Cost, Low-Power Servers

· 2010 the Year of the Microslice Servers

· Linux/Apache on ARM processors

· ARM Cortex-A9 SMP Design Announced

From Datacenter Knowledge: New ARM-Based Server from ZT systems

e: jrh@mvdirona.com

w: http://www.mvdirona.com

b: http://blog.mvdirona.com / http://perspectives.mvdirona.com

Saturday, November 20, 2010 8:06:34 AM (Pacific Standard Time, UTC-08:00)

Comments [2] - Trackback
Hardware

Saturday, November 20, 2010 1:02:28 PM (Pacific Standard Time, UTC-08:00)

Hi James,

These sound a lot like the processors at the core of Netezza's 8x00 series and subsequent 8x50 and 10x00 series database systems. We were shipping MPP database systems up to 6-racks (648 processors) when I left in 2005. I understand they've shipped 10-rack systems since.

According to the literature, the 10x00 systems were based on single-core 800Mhz processors, so they sound a lot like these.

Last year, though, they switched to commodity x86 servers from IBM, much like my current company ParAccel.

Their challenge was selling a fully proprietary system in a world populated by x86 expectations. Now, they are just partially proprietary with their TwinFin boards.

Still, we were able to work wonders with lots of these small/slow chips, and changed the face of the MPP database industry.

One of the benefits of these CPUs is that their memory addressing can be direct, eliminating the extremely expensive overhead of the virtual-to-physical address mapping and TLB misses. The impact can be so severe that the 800Mhz IBM PPC chip (with VM enabled) series is often slower than the lowly 80MHz Motorola PPC chip without VM. It shows up in operations that need to "randomly" touch memory such as hash joins. This is because of the huge cost of TLB misses, which also occurs on x86 processors.

It would be interesting to see if these ARM chips can operate in a manner that prevents these horrid TLB misses.

--Barry Zane, CTO ParAccel

Barry Zane

Saturday, November 20, 2010 2:05:52 PM (Pacific Standard Time, UTC-08:00)

Its great hearing from you Barry. I'm surprised the early Neteeza's where so light on CPU.

The workloads that typically run best on wimpy servers are those that are highly parallalizable. Web servers, memcached, storage but typically not DBs and especially not Oracle.

Thanks for the comment and keep up the good work on ParAccel.

James Hamilton
jrh@mvdirona.com

James Hamilton

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